1. Field of the Invention
The present invention relates to a fabricating process of semiconductor devices. In particular, the present invention relates to a method of evaluating the uniformity of the thickness of the polysilicon gate layer and preventing the problems caused by uneven thickness of the same.
2. Description of Related Art
Along with the rapid development of the integrated circuit industry and the trend of high integration, the size of the entire circuit device is forced to be minimized to meet the requirement. With the increasing demand of the minimized size of the circuit device, the requirements on the surface flatness of wafers have accordingly become more stringent. Hence, it is very important to evaluate and maintain the surface flatness of wafers during the fabricating process.
A chemical mechanical polishing (CMP) process is often used instead of the conventional dry etching process in many fabricating procedures of the integrated circuits. The chemical mechanical, polishing (CMP) process not only ensures the surface flatness of wafers but simplifies the production of the integrated circuits. Thus, the manufacturing yield can be enhanced greatly and the useable surface of wafers of the circuits is significantly increased. However, there exist some problems with the chemical mechanical polishing (CMP) process.
For example, the polysilicon chemical mechanical polishing process (poly CMP) is conventionally used in the manufacturing process of the gates of transistor or memory device. FIGS. 1A through 1C are schematic cross-sectional views showing a conventional method for fabricating the gates of memory device. First, as shown in FIG. 1A, a substrate 100 is provided. The substrate 100 has a memory cell area 102 and a peripheral circuit area 104. Next, a silicon nitride layer 106 and a patterned photoresist layer (not shown) are formed in sequence on the substrate 200. Then, a plurality of trenches 108a and 110a is formed in the substrate 100 by using the patterned photoresist layer as an etching mask, wherein the trench 108a disposed in the memory cell area 102 is more dense and the trench 110a disposed in the peripheral circuit area 104 is relatively sparse. After that, an insulating material is filled in the trenches 108a and 110a to form shallow trench isolation (STI) structures 108b and 110b. Next, as shown in FIG. 1B, the silicon nitride layer 106 and the patterned photoresist layer are removed.
Then, referring to FIG. 1C, a polysilicon layer (not shown) is formed to cover the substrate 100 and the shallow trench isolation (STI) structures 108b and 110b, wherein the polysilicon layer is used for forming gate structures. The polysilicon layer is planarized by performing polysilicon chemical mechanical polishing process and then polysilicon layers 112 and 114 are formed in the memory cell area 102 and the peripheral circuit area 104 respectively. Since the polishing rate of the polysilicon chemical mechanical polishing process is relevant to the size and density of the patterns on wafers. It is caused by the differences of partial pressures applied on the layers, meaning the different pressures caused by the same polishing force will vary on different patterned areas. Therefore, when performing the polysilicon chemical mechanical polishing process, it is easily to over polish on the surface of the wafers located in the low pattern density area (the peripheral circuit area 104) and causing the recession of the polysilicon layers in the area, which often referred as dishing effect. Subsequently, the thickness t1 of the polysilicon layer 112 and thickness t2 of the polysilicon layer 114 are not uniform and thus the entire surface of the wafer is uneven.
In specific, the poor thickness uniformity problem of the mentioned polysilicon layers will significantly affect the performance of the device. Besides, in the subsequent fabricating process, problems caused by the poor thickness uniformity of polysilicon layers will also affect the lithography process and etching process that preformed after the process of forming the gate structures. These problems will affect the reliability of the manufacturing process.